Kepler Computing's CEO drops an interesting roadmap for next-gen chip efficiency:
First wave: aggressive 3D stacking beyond HBM. Instead of radical material switches, stack silicon vertically to cut interconnect latency and power draw. Think chiplets taken to the extreme—logic, memory, analog all layered tight.
Second wave: multi-material integration. Once 3D architecture is maxed out, they'll pull in compound semiconductors (GaN, InP, etc.) to push energy efficiency another order of magnitude.
The take: evolutionary 3D first, then revolutionary materials. Practical path vs. moonshot bets on entirely new substrates. If they execute, this could bridge the gap between current node scaling limits and exotic future tech without betting the farm on unproven materials science.
First wave: aggressive 3D stacking beyond HBM. Instead of radical material switches, stack silicon vertically to cut interconnect latency and power draw. Think chiplets taken to the extreme—logic, memory, analog all layered tight.
Second wave: multi-material integration. Once 3D architecture is maxed out, they'll pull in compound semiconductors (GaN, InP, etc.) to push energy efficiency another order of magnitude.
The take: evolutionary 3D first, then revolutionary materials. Practical path vs. moonshot bets on entirely new substrates. If they execute, this could bridge the gap between current node scaling limits and exotic future tech without betting the farm on unproven materials science.