DeepSeek has decided to push the computing chips into the deep waters of an autonomous compute infrastructure base. A roughly 30 billion RMB budget for expanding compute power—together with the company’s earliest planned entry in the fourth quarter using Huawei’s next-generation Ascend training chips—has officially shifted the turning point for large-model R&D from earlier phases of inference-oriented adaptation to the main battleground of training: a Wan-Cards cluster where tens of thousands of cards run continuously under high load.
This aggressive shift at the infrastructure level is reshaping the risk appetite along the tech track and the structure of capital positions. Moving model scale from 200 billion parameters to 800 billion parameters multiplies the throughput requirements for chip clusters by orders of magnitude. The dual squeeze of supply-chain uncertainty overseas and the pressure of capital expenditure prompts leading teams to proactively absorb migration costs, accelerating a revaluation of the domestic compute-power supply chain.
The real test of this high-stakes bet lies in the tolerance space for engineering execution. Inter-chip interconnect communication across tens of thousands of chips, optimization of the underlying software stack, and training stability sustained for months—any minor shortcoming will be dramatically amplified by large-model training. Both industry and market capital are holding their breath, waiting for the real backtest feedback that the first round of large-scale, long-cycle training will provide after the new chips are delivered in the fourth quarter.
This aggressive shift at the infrastructure level is reshaping the risk appetite along the tech track and the structure of capital positions. Moving model scale from 200 billion parameters to 800 billion parameters multiplies the throughput requirements for chip clusters by orders of magnitude. The dual squeeze of supply-chain uncertainty overseas and the pressure of capital expenditure prompts leading teams to proactively absorb migration costs, accelerating a revaluation of the domestic compute-power supply chain.
The real test of this high-stakes bet lies in the tolerance space for engineering execution. Inter-chip interconnect communication across tens of thousands of chips, optimization of the underlying software stack, and training stability sustained for months—any minor shortcoming will be dramatically amplified by large-model training. Both industry and market capital are holding their breath, waiting for the real backtest feedback that the first round of large-scale, long-cycle training will provide after the new chips are delivered in the fourth quarter.