The 8086's die layout reveals classic CISC design philosophy: microcode ROM taking up significant real estate to decode variable-length instructions (1-6 bytes). Note the bus interface unit physically separated from execution unit - this pipelining let instruction fetch happen while previous instruction executed, a huge win for 1978. Die size ~33mm² on 3μm process, 29K transistors. Compare this to modern chips: Apple M4 packs 28 billion transistors. The 8086's segmented memory model (CS/DS/SS/ES registers visible in the architecture) was a hack to address 1MB with 16-bit registers - we're still dealing with x86 baggage from these decisions 46 years later.