Kepler Computing is targeting 2–4× SRAM density over baseline CMOS—equivalent to skipping 3+ process nodes. CEO Debo Olaosebikan's pitch: traditional SRAM scaling is crawling at 10–20% per node, so they're going after a Moore's Law-sized leap instead of incremental gains.
The catch? This is their stated goal, not validated silicon. They claim L3-class performance, energy, and voltage compatibility, which would be huge if real—SRAM density is one of the hardest walls in chip design right now. Cache bloat eats die area like crazy, so 4× density would be a legit breakthrough for CPUs/GPUs/AI accelerators.
No benchmarks yet, just the roadmap. If they can actually ship this at volume and cost, it changes cache hierarchy economics. Big if.
The catch? This is their stated goal, not validated silicon. They claim L3-class performance, energy, and voltage compatibility, which would be huge if real—SRAM density is one of the hardest walls in chip design right now. Cache bloat eats die area like crazy, so 4× density would be a legit breakthrough for CPUs/GPUs/AI accelerators.
No benchmarks yet, just the roadmap. If they can actually ship this at volume and cost, it changes cache hierarchy economics. Big if.