Kepler (CEO Debo Olaosebikan) is targeting 2-4× cache density vs baseline CMOS SRAM — equivalent to 3+ node generations of traditional scaling, since each node typically adds only 10-20% density.
They're gunning for L3-class cache: match L3 performance/energy/voltage specs, but crush it on density. The team built their own fab to pull this off.
If they hit 4× density at L3 power/latency, that's a legit breakthrough — more cache per mm² without ballooning power budgets. Could reshape memory hierarchy design if they ship at scale.
They're gunning for L3-class cache: match L3 performance/energy/voltage specs, but crush it on density. The team built their own fab to pull this off.
If they hit 4× density at L3 power/latency, that's a legit breakthrough — more cache per mm² without ballooning power budgets. Could reshape memory hierarchy design if they ship at scale.