SemiAnalysis said on October 15 that ASML has not officially announced a related product, but patents, news reports, and the company’s roadmap all point to work on hybrid bonding equipment. According to ChainCatcher, the article’s author believes ASML may first launch a more difficult chip-to-wafer hybrid bonding tool as an extension of its vertical integration strategy.

The report said ASML filed 27 bonding patent families between December 2022 and November 2024, with most focused on chip-to-wafer applications. It also cited a March report from The Elec saying ASML had begun hybrid bonding architecture design with Prodrive Technologies and VDL ETG.

The article said wafer-to-wafer hybrid bonding is already used in image sensors and 3D NAND, while chip-to-wafer hybrid bonding is currently used only in logic chip mass production, including AMD’s hybrid-bonded V-Cache shipments since 2022 and TSMC’s SoIC. SoIC currently has a pitch of about 6 microns and aims to reach 4.5 microns by 2029. Besi is currently the only supplier with chip-to-wafer mass-production tools, and its logic business is mainly concentrated at TSMC and Intel.