3D chip stacking is hitting a thermal ceiling — and it's forcing a redesign of the entire roadmap.
ZDNet Korea reports more fabless customers are now asking Samsung Foundry about 3D IC options. The reason is simple: planar shrink is running out of area efficiency. So the industry is moving toward stacking memory on logic or mixing dies vertically. Coasia Semi already ships a volume part that puts DRAM directly on a logic SoC.
But there's a structural problem — heat. Inner dies in a 3D stack can't dissipate thermal energy effectively. In DRAM, that causes leakage, which forces shorter refresh cycles and cuts system performance. For years, this thermal prison kept designers from using the full potential of vertical integration.
Now hardware and software cooling tech is finally catching up. One industry source said chips no longer have to be detuned as aggressively just to stay within temperature limits.
Jeon Deok-ho of Prime Mask Korea flipped the sequence: stacking became mandatory first because 2D shrink hit a wall. Cooling then had to follow so the stack could actually function in production.
This means 3D IC volume will track the thermal path as much as the interconnect roadmap.
The real question: how many 3D designs are sitting on paper right now, waiting for cooling to be qualified — versus designs already constrained by today's heat limits?
ZDNet Korea reports more fabless customers are now asking Samsung Foundry about 3D IC options. The reason is simple: planar shrink is running out of area efficiency. So the industry is moving toward stacking memory on logic or mixing dies vertically. Coasia Semi already ships a volume part that puts DRAM directly on a logic SoC.
But there's a structural problem — heat. Inner dies in a 3D stack can't dissipate thermal energy effectively. In DRAM, that causes leakage, which forces shorter refresh cycles and cuts system performance. For years, this thermal prison kept designers from using the full potential of vertical integration.
Now hardware and software cooling tech is finally catching up. One industry source said chips no longer have to be detuned as aggressively just to stay within temperature limits.
Jeon Deok-ho of Prime Mask Korea flipped the sequence: stacking became mandatory first because 2D shrink hit a wall. Cooling then had to follow so the stack could actually function in production.
This means 3D IC volume will track the thermal path as much as the interconnect roadmap.
The real question: how many 3D designs are sitting on paper right now, waiting for cooling to be qualified — versus designs already constrained by today's heat limits?