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叮噹-Doraemon
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Can AI run directly into the heart of financial core systems? IBM mainframe chips achieve a major breakthrough: a single chip natively supports both IBM and Arm architectures
AI News Flash: At Hot Chips, IBM unveiled a new-generation dual-architecture host processor. For the first time, a single chip can natively run both IBM host instruction sets and Arm instruction sets, enabling nanoscale-speed switching between the two architectures without simulation or conversion.
Key highlights of the core:
① Dual-architecture on one die: each processor core can natively execute both IBM Z and Arm instructions, enabling nanoscale switching. No separate heterogeneous cores or traditional simulation methods are used.
② Top-tier process and performance: built using an advanced 2-nanometer manufacturing process, with a clock speed exceeding 5.7GHz. Includes an AI inference accelerator and a large on-chip cache.
Key highlights of the core:
① Dual-architecture on one die: each processor core can natively execute both IBM Z and Arm instructions, enabling nanoscale switching. No separate heterogeneous cores or traditional simulation methods are used.
② Top-tier process and performance: built using an advanced 2-nanometer manufacturing process, with a clock speed exceeding 5.7GHz. Includes an AI inference accelerator and a large on-chip cache.
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