Nvidia's next-generation AI platform Feynman is targeted for mass production in the second half of 2028 and is expected to use TSMC's A16 process, along with SoIC 3D stacking and CPO technology. According to ChainCatcher, the report said the Rubin generation focuses on multi-chip and HBM integration, while Feynman moves further toward 3D chiplets, SoIC, and CPO.

TSMC is accelerating related capacity expansion, with its SoIC monthly output target raised from 20,000 wafers by the end of 2026 to 50,000 wafers by the end of 2027. The company is also speeding up construction at its Chiayi AP7 and Tainan AP8 fabs. AP7 has eight planned phases, with P1 and P2 already in equipment installation, P3 and P4 having received building permits, and P5 through P8 still in planning.

The AP7 site will initially mass-produce Apple's WMCM and later add SoIC, CoPoS, and CPO lines based on customer demand. The report said Nvidia has rapidly shifted R&D and supply-chain resources toward the Feynman platform, while the spillover effect of TSMC's advanced packaging orders continues to expand, with Advanced Semiconductor Engineering becoming a key foundry assembly and test supplier for Nvidia's CoWoS and CPO orders.

Nvidia's Feynman platform is expected to push NVLink interconnect bandwidth above 1 PB/s, up from Rubin Ultra's 520 TB/s. TSMC's COUPE technology uses SoIC to integrate EIC and PIC in 3D to create an optical engine, moving optical-electrical conversion from traditional circuit boards into the package architecture. Since 2026, Nvidia has invested more than $40 billion in its AI ecosystem across models, wafer manufacturing, data centers, and optical communications.