Authors: Ray Wang, Myron Xie, Dylan Patel, and others
Compiled by: Deep Tide TechFlow
Deep Dive: Changxin Storage (CXMT) is set to hit the Sci-Tech Innovation Board, poised to become the largest semiconductor IPO in China's history. Founded in 2016, this company kicked off by acquiring patents and talent from the bankrupt German DRAM manufacturer, Qimonda. With nearly a decade of capital infusion tolerated by the Hefei government despite losses, they are expected to turn a profit in 2025, with Q1 2026 revenue projected to hit $7.3 billion. The lengthy report by SemiAnalysis breaks down Changxin's tech roadmap, financials, HBM challenges, and IPO structure—essential reading for anyone looking to grasp the position of China's memory chip industry.
The SemiAnalysis team described as early as late 2024 in its newsletter the enormous demand for memory created by AI inference and agent workflows. Since then it has published multiple in-depth memory reports and continuously tracked CXMT Storage and China’s compute ecosystem. With CXMT Storage preparing to list in the coming months, a dedicated deep-dive research report is necessary. CXMT is very likely to become the biggest semiconductor IPO in China and also a milestone for this top-tier Chinese memory maker. From here, CXMT’s competition with Samsung, SK hynix, and Micron will only become fiercer.
Silicon Valley returnees to China
CXMT Storage’s founder, Zhu Yiming. He graduated in 1994 with a bachelor’s degree in physics from Tsinghua University, then went on to pursue electrical engineering at Stony Brook University in New York State. He worked in Silicon Valley for many years and became a project leader at MoSys (Monolithic System Technology) around 2001. In 2005, Zhu Yiming returned to China with a set of SRAM patent portfolios and $100,000 in seed funding, founding GigaDevice (兆易创新). It later became one of the world’s top NOR Flash suppliers. But the global NOR Flash market is far smaller than DRAM or NAND Flash. Zhu Yiming had bigger ambitions, so he chose the DRAM track.
DRAM isn’t a game that fabless companies can play. DRAM consumes capital, has extremely strong patent barriers, and depends heavily on manufacturing capabilities. By 2016, only three survivors remained in the entire industry: Samsung, SK hynix, and Micron. The moat built from decades of accumulated patents and capital prevented any new player from breaking through. Zhu Yiming’s SRAM patents and GigaDevice’s NOR Flash business cannot provide DRAM storage-cell design, DRAM process know-how, or any way to bypass the incumbents’ patent lockout. So when Zhu Yiming and the Hefei municipal government launched the DRAM project “506 Project” in 2016 (i.e., what later became CXMT Storage), the core technologies had to be obtained from outside.
The source is a German company that has already gone out of business.
DRAM foundations: the Qimonda legacy
The deceased company is none other than Qimonda. Qimonda went bankrupt in January 2009 due to the global financial crisis and the subsequent DRAM price collapse, but at that time it was a leading DRAM maker in Europe. As a subsidiary of Infineon, tracing back to Siemens, Qimonda offered a rare alternative: a deep library of DRAM patents and a set of storage-cell architectures—both outside the Samsung–Hynix–Micron triangle.
In June 2015, Polaris Innovations, a subsidiary of Canadian patent operating company WiLAN, bought about 7,000 Qimonda patents and applications from Infineon for roughly EUR 30 million. In December 2019, Polaris and CXMT signed an agreement authorizing a large batch of DRAM patents. CXMT executives have publicly said they obtained about 2.8TB of Qimonda technical documentation, which became the foundation of CXMT’s DRAM business.
One key technology CXMT inherited and developed from Qimonda is the 46nm-class BWL (Buried Wordline) storage cell, which it pushes forward to the 10nm-class level. BWL is a core architectural innovation. In conventional approaches, the gate of the access transistor is routed on the surface of the wafer; in BWL, the gate is embedded in a trench below the bit lines. This delivers three benefits: it shrinks the storage cell layout to 6F² (traditional is 8F²); it extends the channel length without consuming surface area to suppress short-channel leakage (which affects data retention); and it reduces parasitic gate-to-bit-line capacitance. Embedded wordlines plus stacked capacitor—this is the architecture the three major memory giants use today. Back then, Qimonda’s choice to stick with the trench approach preserved the know-how for stacking/BWL—and CXMT picked up exactly that.
Talent: from frozen blueprints to living R&D capability
Besides patents, the longer-lasting asset that CXMT gained from Qimonda’s collapse was its engineers. Qimonda built a research and development center in Xi’an with 400–500 engineers, one of Qimonda’s largest R&D hubs outside Germany. After Qimonda went bankrupt, although the entire Xi’an R&D center was acquired by Unigroup, the broader spread of talent benefited CXMT.
CXMT also successfully attracted a senior engineer, Karl-Heinz Kuesters, from Qimonda’s German headquarters. Kuesters served as technical and pre-research vice president at Siemens, Infineon, and Qimonda for up to 24 years. The pre-research production line he led is precisely the stacked capacitor approach—that is the architecture CXMT actually uses. He joined CXMT as a technical adviser, and EE Times described Kuesters as CXMT’s “ace.” What Kuesters brings is tacit know-how that cannot be carried by patents and the 2.8TB of documents: his experience leading DRAM development for two decades, allowing him to tell CXMT’s engineers which of Qimonda’s designs to keep, which to discard, and how to take storage cells proven in the lab into mass production. This kind of integration and yield judgment does not exist in any patent literature.
The U.S. side follows a similar pattern. Ping Er-xuan, CXMT’s Vice President for future technology assessment—i.e., the public explainer of the “46nm to 10nm” roadmap—is not from Qimonda. Instead, he built his U.S. career at Micron, SanDisk, and Applied Materials, with deep accumulation in memory and materials technologies.
CXMT also recruits a large number of talent from South Korea and Taiwan. Korean prosecutors have reportedly filed charges against former Samsung employees for leaking technology, and dozens of Korean engineers have reportedly worked at CXMT. Taiwan is similar: CXMT continuously poaches top equipment and process engineers with generous compensation packages.
This is the key to understanding CXMT’s path. Qimonda’s patents were always limited and would expire. What allowed CXMT to progress from G4 to G5 and then to HBM was the concentration of人才 capability—locally trained talent, Chinese engineers who returned after working at foreign firms, and a small number of overseas experts—not documentation. The legacy was just the starting point; talent turned that legacy into an engine for independent R&D. But that engine took nearly a decade to become profitable. The question is: who has the patience to keep funding it indefinitely?
Patient capital of state-owned venture investors
CXMT’s success is hard not to attribute to strong support from both local and central governments in China. A classic example is Hefei. Hefei is a major hub for technological innovation in China. Over the past two decades, it has incubated a batch of successful companies using a “patient state-owned venture investment” model: BOE (a global top-tier display panel maker) and NIO (a leading electric-vehicle manufacturer). Now it is CXMT’s turn to build its storage business.
Hefei’s municipal government did two key things for CXMT.
First, build a local supply chain around the factory for CXMT. Hefei’s approach is: take large equity stakes in key “chain-leader” companies, and then attract the rest of the industrial chain to come along. The display panel industry did this for BOE, the electric vehicle industry did it for NIO, and since 2016 it has been replicated for CXMT. Around CXMT’s plant in Hefei’s Xuangang Economic Zone, the government built a dense local industrial cluster. The packaging and testing factories, Peidun and Xinfeng, are just across a wall from CXMT’s plant, and Xinfeng’s revenue comes from more than 99% from CXMT. Guanggang Operation’s onsite supply of bulk gases provides most of what CXMT needs, and Zhivi Semiconductor (under the flag of Purest Technology) provides wafer-recycling capacity in Hefei Xinzhan High-Tech Zone. State-owned venture investors also directly control the upstream chip molding equipment maker Wenyi Technology.
Second, Hefei’s state-owned capital is willing to lose money for a long time. Unlike private equity funds that must deliver returns to LPs on schedule, Hefei’s state-owned venture investment is ultimately backed by municipal government and state-owned entities in development zones—there is no “exit clock.” They keep cashing in to a company that did not achieve its first annual profit until 2025 and has accumulated losses of roughly RMB 36.65 billion, losing for almost a decade. The “506 Project” launched in 2016—its first phase had about 80% of the funding (RMB 14.4 billion/18.0 billion) from Hefei’s state-owned venture investment. In later rounds of financing, although Hefei’s state-owned capital was diluted, it never sold down and never exited. At the IPO, the largest shareholder, Hefei Qinghui Electric, held 21.67%, and the combined state-owned venture investment stake was over 30%. The willingness to treat a wafer fab as a decade-long bet rather than as fund-cycle returns—this is the catalyst that enables both technology and talent to depend on sustained support.
From inherited legacy to independent capability
All three clues together make CXMT’s first decade clear. Qimonda provided the foundation: an authorized patent library and storage-cell architecture from outside the big three triangle. Talent provided the momentum: key figures like Kuesters and Ping, plus returnees who came back from U.S. giants, and controversial hires poached from South Korea—who turned frozen blueprints into processes that could be continuously advanced. Then the Hefei government provided what the other two needed but could not create on their own: capital, patience, and a localized supply chain. None of the three was optional.
Next, we discuss CXMT’s financials, technology, and equipment ecosystem.
The next step ten years later: an IPO in a supercycle
CXMT’s story over the past decade is impressive, but it may only be an early chapter of a longer narrative. The company is preparing one of the biggest semiconductor IPOs in China in recent years—and possibly the most watched semiconductor listing globally this year. In December 2025, the Shanghai Stock Exchange formally accepted CXMT’s application for a STAR Market listing. Before that, market rumors in 2024 and 2025 had persisted about the company preparing an IPO. The latest progress is that on May 27, CXMT submitted a registration application to the CSRC and is now in the final review stage.
CXMT’s IPO prospectus discloses a large amount of information that had previously been unavailable. By combining it with SemiAnalysis’s Memory Model, we can make more precise judgments about CXMT’s current position and future trajectory.
At a high level, measured by nearly every metric, CXMT is the world’s fourth-largest DRAM manufacturer and is widening its lead over Tier-2 memory makers. In full-year 2025, CXMT’s revenue grew 156% year over year to about $8.6 billion, compared with about $3.3 billion in 2024 and about $1.2 billion in 2023. Net profit also turned positive for the first time, reaching $1 billion. Even so, CXMT’s 2025 revenue is still far below Samsung (about $72.3 billion), SK hynix (about $52.1 billion), and Micron (about $37.2 billion) DRAM revenue.
Caption: Comparison of global DRAM vendors’ revenues (Source: SemiAnalysis Memory Model)
In Q1 2026, CXMT reported revenue of $7.3 billion, up about 700% year over year; quarterly revenue was already close to 2025 full-year levels. Operating profit margin also expanded sharply, reaching around 70%.
SemiAnalysis believes this is only the beginning. Based solely on what is disclosed in the prospectus, the company’s revenue in the first half of 2026 is expected to grow 7x year over year, exceeding $16 billion. For all of 2026, SemiAnalysis estimates CXMT revenue could exceed $50 billion. If that happens, it means the company’s revenue will have doubled every year since 2023, and the year-over-year growth in 2026 would exceed 6x.
The driving force behind this explosive growth is less about technology or market share and more about the cycle itself. Look carefully at the data: in Q1 2026, CXMT’s bit shipments increased only 11%, but ASP (average selling price) rose by about 57%. In contrast, the quarter-on-quarter ASP increases in Q3 and Q4 2025 were 63% and 68%, respectively. What truly boosts performance is the explosive price surge, not a significant capture of market share from peers. Measured by bit shipments, SemiAnalysis’s model shows CXMT’s market share rising from 9% in 2025 to 12% in 2027. A 3-percentage-point increase may look small, but in a market where SemiAnalysis forecasts the scale of 2027 to be close to $1 trillion, it is huge.
Caption: Trend in CXMT’s ASP and bit shipment volumes (Source: SemiAnalysis Memory Model)
The misconception behind the “Chinese memory shocks the market” narrative
For readers who have not yet deeply tracked CXMT or the memory market, a more interesting discovery is CXMT’s pricing compared with industry leaders. Based on data from the Memory Model, CXMT’s DRAM ASP challenged a common misconception: that Chinese memory is structurally cheaper and will disrupt the market by pushing down global prices. That may have been true in some cases in the past, but it does not hold accurately in this cycle.
Take Q1 2026 as an example: CXMT’s DRAM ASP is only about 5–10% lower than Samsung, SK hynix, and Micron. SemiAnalysis expects this direction will not change for all of 2026, but the gap will gradually widen. The widening is not due to inherent pricing differences, but to changes in product mix. Top vendors ship a higher proportion of server DRAM and HBM, and server DRAM has a better pricing outlook than consumer DRAM.
By the end of 2027, SemiAnalysis expects server DRAM and HBM to account for more than 50% of DRAM terminal market demand. Because server DRAM and HBM command higher per-GB prices, the leading vendors will widen their ASP gap versus CXMT—especially considering that HBM prices are expected to rise sharply in 2027.
Caption: Comparison of DRAM vendors’ ASP (Source: SemiAnalysis Memory Model)
Profit margins: the gift of the cycle
A strong tailwind from ASPs significantly improves CXMT’s margins. CXMT’s full-year 2025 gross margin reached 37.8%, close to Samsung’s 39.4% and Micron’s 39.8%, but far below SK hynix’s 60.4% (SK hynix benefited from a higher HBM shipment mix). CXMT’s gross margin of about 38% represents a huge rebound from -113% in 2023 and -4.7% in 2024. 2025 is not only a historical high for CXMT’s gross margin, but also the first time the company achieves positive gross margin.
Caption: Comparison of DRAM vendors’ gross margins (Source: SemiAnalysis Memory Model; company reports)
Entering 2026, margins improve further. In Q1, the operating margin reached 70%; for the same period, SK hynix was 73%, Samsung 81%, and Micron 84%. Beyond ASP growth, CXMT’s margin improvement also benefits from its product structure being almost entirely focused on commodity DRAM—under current conditions, the profit margins of commodity DRAM are actually higher than those of HBM. According to the prospectus, about 99% of CXMT’s bit shipments in 2025 are traditional LPDDR and DDR products, with HBM contributing very little to revenue and profit.
Caption: Comparison of DRAM vendors’ operating profit margins (Source: SemiAnalysis Memory Model; company reports)
A simple DDR5 unit-cost breakdown makes the picture clearer. SemiAnalysis found that CXMT’s DDR5 cost per bit is still more than 30% higher than the three major incumbents. But because DDR5 pricing in Q1 2026 is already very strong, CXMT’s gross margin has still been pushed up to above 70%. This means CXMT’s profit-margin improvement is driven mainly by pricing, not by a substantive improvement in product competitiveness or cost structure.
Caption: Comparison of DDR5 cost per bit (Source: SemiAnalysis Memory Model)
Capacity expansion: nearing Micron
In addition to record profits, CXMT is also catching up on capacity. By the end of 2026, SemiAnalysis expects CXMT to reach around 350,000 wafers per month in wafer production capacity—just slightly below Micron’s roughly 385,000 wafers per month. Ranked by wafer capacity, CXMT is poised to become the industry’s third-largest memory supplier.
Caption: Comparison of global DRAM vendors’ wafers per month (Source: SemiAnalysis Memory Model)
But CXMT still has a significant gap with the two leading giants: Samsung at about 720,000 wafers per month, and SK hynix at about 595,000 wafers per month. By 2027, with Shanghai Phase 1’s initial ramp-up and full production in Hefei and Beijing, CXMT’s capacity could reach roughly 420,000 wafers per month—about 17% of global DRAM capacity, up from about 13% in 2025. Measured by bit shipments, its share would rise from 9% in 2025 to 12% in 2027.
By 2028, as Hefei reaches full production and the two phases in Shanghai continue ramping up, SemiAnalysis expects CXMT to reach about 500,000 wafers per month—around 17% of global DRAM supply.
Caption: CXMT Hefei plant capacity (Source: SemiAnalysis Memory Model)
Concerns about oversupply: don’t worry for at least the next two years
Given CXMT’s increasingly important role in global DRAM capacity, as in every past cycle investors worry that Chinese suppliers could cause supply-demand imbalance. SemiAnalysis believes this concern is being exaggerated at least over the next two years. After incorporating incremental capacity from CXMT and other memory vendors and bit shipments—and assuming utilization rates of 90% or higher—DRAM supply will still be extremely tight.
Caption: DRAM supply-demand balance (Source: SemiAnalysis Memory Model)
Looking only at CXMT’s capacity expansion pace: in 2026–2028, it adds roughly 85,000, 70,000, and 80,000 wafers per month each year, while Samsung adds 15,000/50,000/110,000, SK hynix 60,000/60,000/90,000, and Micron 30,000/90,000/115,000. Even after counting these additional capacities, DRAM will still be in shortage by high single-digit percentages in 2026; the gap will widen to low-to-mid twenties by 2027. SemiAnalysis has previously explained in detail why DRAM could remain in supply shortfall until 2028.
CXMT lacks the ability to irrationally accelerate capacity expansion beyond the current pace to disrupt the market, because wafer-fab construction cycles are too long. The current extremely favorable pricing environment is precisely the main driver behind CXMT’s performance explosion—CXMT of course hopes that this environment continues. SemiAnalysis has also not seen any signs of such possibilities in the wafer-fab construction progress it tracks. But it is worth emphasizing that when the Shanghai plant reaches full production, total wafer capacity could exceed 400,000 wafers per month.
HBM: CXMT’s predicament
In the HBM area, CXMT’s wafer allocation is extremely limited. As of end-2025, of CXMT’s capacity of about 2.65 million wafers per month, only roughly 5,000 wafers are allocated to HBM. SemiAnalysis expects this figure to rise to about 30,000 wafers by end-2026 and about 55,000 wafers by end-2027. This matches the prospectus disclosure that about 99% of 2025 revenue came from DDR and LPDDR.
Caption: CXMT HBM wafer capacity allocation (Source: SemiAnalysis Memory Model)
But this allocation pattern may change. China’s push for AI compute to be independently controllable could conflict with the company’s commercial priorities, and this pressure is expected to strengthen over time. SemiAnalysis has included in its forecasts a factor that the government will guide CXMT to tilt capacity toward HBM, estimating that HBM capacity will accelerate expanding in 2027 and 2028. CXMT’s projected HBM capacity would reach 55,000 wafers per month in 2027 and 100,000 wafers per month in 2028, with its share of global HBM wafer supply rising from 1% in 2025 to 12% in 2028.
It’s important to remember that unlike other memory makers, CXMT is not only a company that matters economically and technologically—it is also a strategic asset that a nation can use to advance prioritized policy goals.
From a short-term business logic standpoint, it is reasonable for CXMT to prioritize allocating capacity to commodity DRAM rather than HBM. Commodity DRAM’s profit margin is currently significantly higher than CXMT’s HBM products, and with the same wafer area the bit output is more than 3x that of HBM. In the stage when HBM technology is still not mature, pouring large investments into HBM capacity would consume scarce wafer capacity that could otherwise be used for higher-margin commodity DRAM with higher output. But China must push forward with an HBM layout because HBM sales to China are strictly constrained by U.S. export controls, and Korean vendors’ shipments to China rely only on maintaining flows through a few loopholes.
HBM technology gap
On technical readiness, SemiAnalysis believes CXMT is still struggling to achieve stable mass-production of HBM3 8-hi, while 12-hi faces even greater challenges.
On the front end, CXMT has made progress in production stability for its **G4 (equivalent to the 1z node)**, and most DRAM output in 2026 will be based on the G4 process. But the DRAM core chips used for HBM require a larger die area and stricter performance requirements, so the wafer-sort yield at the front end should be significantly lower than for bulk DRAM. SemiAnalysis believes that front-end yield is still a major challenge for CXMT and that the gap versus peers remains large. Although G4 yields have improved, inferred from lower profit margins in 2024 and 2025, they may still be below the 85–90% mature yield level typical for the 1z node industry. This suggests that equipment constraints and manufacturing experience remain ongoing obstacles CXMT needs to overcome.
Caption: CXMT DRAM process node roadmap and yields (Source: SemiAnalysis Memory Model)
The next generation process node, G5 (equivalent to the 1a node). In theory, like Micron’s 1a, it may be possible to advance without further reliance on EUV lithography, but it will face increasingly large challenges in manufacturing and design. These challenges will be further exacerbated when applying this node to HBM DRAM die.
Die stacking is the biggest obstacle for CXMT’s HBM. HBM stacking usually brings serious technical problems: thermal stress, die cracking, warpage, bonding defects, and yield losses from multi-layer stacking. As CXMT moves from HBM3 8-hi to HBM3 12-hi and even HBM3E, these issues become even more severe because CXMT still lacks sufficient manufacturing experience with 12-hi and above.
Stacking challenges are not unique to CXMT. Top-tier vendors also face issues with 12-hi HBM4, such as die cracking, thermal management, and yield losses. 16-hi—and even 20-hi—is even more troublesome. One reason Rubin Ultra is expected to adopt 12-hi HBM4E instead of 16-hi is supply: 16-hi requires more DRAM wafers, is harder to manufacture, causes greater wafer loss, and provides less effective bit supply.
SemiAnalysis believes CXMT is increasingly likely to skip HBM3 and focus directly on HBM3E 8-hi and 12-hi. There are two reasons: first, customers in the 2027 time window need more competitive HBM products; second, mainstream accelerators at that time will be equipped with HBM3E, HBM4, and HBM4E.
Caption: Global HBM roadmap comparison (Source: SemiAnalysis Memory Model)
For backend packaging, while it is still debated whether CXMT uses MR-MUF or TC-NCF, the packaging challenge is relatively more controllable because the company and its outsourced assembly and test partners face fewer restrictions under export controls. CXMT has long worked closely with top OSATs such as Tongfu Microelectronics. Backend capabilities should improve gradually, but there is still a gap versus top-tier memory vendors.
Based on existing manufacturing challenges, SemiAnalysis models CXMT’s front-end and back-end yields for HBM3 8-hi at about 35% and 70%, respectively, for a combined yield of only about 25%. HBM3 12-hi or HBM3E 12-hi should have an even lower combined yield because stacking and bonding are more difficult. With yields at that level, for the same wafer capacity, CXMT’s HBM output will be far below that of top-tier vendors. Even more critical is that the profit margin of the HBM produced would be extremely low—especially compared with commodity DRAM under the current pricing environment.
CXMT’s HBM predicament is also reflected in product penetration. SemiAnalysis believes that perhaps only Huawei, Cambricon, and a few emerging Chinese AI-chip startups will use CXMT’s HBM—but adoption ratios could be high. Domestic AI accelerator vendors will, where possible, still prefer foreign HBM3 and even HBM3E, whether through any available channels or inventories before the December 2024 export-control restrictions. As Chinese domestic cloud vendors rapidly increase capex and build compute capacity, domestic HBM demand is also growing quickly.
One notable exception: Huawei and CXMT will develop customized HBM that is not based on JEDEC standards and PHY, which will help make up for bandwidth disadvantages.
The HBM supply constraints facing China may be even more severe than what the slower-than-domestic-HBM development itself implies. The supply from the three major HBM suppliers is already tight, and according to U.S. export controls from December 2024, they have been restricted from selling HBM2E and more advanced HBM products to China. In a tight supply environment, these vendors are less willing to take risks and violate rules to ship to China.
But the HBM transshipment and smuggling make things even more complex. SemiAnalysis learned that some Chinese companies still obtain HBM3 through various channels. Transshipment via overseas offices or cooperation partners in third countries is still one route; some OSATs or intermediaries in third countries also facilitate these flows. Some entities export partially assembled systems or modules (not considered finished GPUs or ASICs, so exports to China are still allowed); then the HBM is disassembled and re-packaged onto domestic GPUs or ASICs.
What the IPO structure reveals
CXMT may become one of China’s largest semiconductor IPOs, and its equity structure is more worth attention than the book financials. CXMT reported 2025 consolidated net profit of RMB 7.14 billion, but net profit attributable to shareholders of the parent company was only RMB 1.87 billion—74% attributable to minority interests.
The reason lies in the equity structure. CXMT holds only 30.68% of the economic interest in CXMT New Bridge and 31.72% of the economic interest in CXMT Jidian Beijing, but through a long-term concerted action arrangement it controls voting rights of 73.01% and 75.32%, respectively. This allows the company to consolidate wafer fabs it effectively does not own most of. As a result, the consolidated data overestimates the profits that public shareholders can actually receive by roughly four times.
Caption: CXMT consolidated profit vs attributable profit (Source: SemiAnalysis Memory Model; company reports)
The same voting structure also makes the company’s statement that it has “no controlling shareholder and no de facto controller” lack persuasiveness (listed as a formal governance risk in the prospectus). CXMT exercises majority voting control over wafer fabs through concerted-action agreements. After the listing, the National IC Industry Investment Fund Phase II, along with state-owned entities from Hefei and Anhui, will hold more than 30% in total. This arrangement appears intended to manage export-control risk and foreign investors’ perceptions—at a time when CXMT’s relationship with the Chinese government is being scrutinized the most.
Caption: Diagram of CXMT’s equity structure (Source: SemiAnalysis Memory Model; company reports)
Valuation: an undervalued floor price
CXMT plans to raise RMB 29.5 billion (about $4.1 billion), representing 10–15% of the company’s total share capital after listing. Raising funds fully through the IPO means: at 10% dilution, about RMB 4.41 per share; at 15% dilution, about RMB 2.78 per share (the financing price in June 2025 was RMB 2.63). At the lower end of the price range, there is almost no premium versus the previous round. This is despite already achieving $7.3 billion in revenue and $4.8 billion in net profit in Q1 2026. A price of RMB 2.78 implies a valuation of about RMB 197 billion (about $27 billion), only around 1.8x the annualized attributable-to-parent profit for the first half of 2026. SemiAnalysis believes this valuation floor is far too low and that actual pricing should be much higher.
Caption: CXMT IPO valuation analysis (Source: SemiAnalysis Memory Model; company reports)
Use of funds: Focus on bulk DRAM; no mention of HBM
The RMB 29.5 billion fund-raising purpose strengthens CXMT’s current priorities. Of that, RMB 20.5 billion (69.5%) goes to wafer production lines and DRAM technology upgrades, while RMB 9.0 billion (30.5%) goes to forward-looking DRAM research. The prospectus does not disclose dedicated HBM projects, nor does it even mention HBM. The project descriptions focus on an updated process platform, product iteration, and migrating existing lines toward mid-to-high-end DRAM. The core role of the IPO is to strengthen CXMT’s DRAM manufacturing and technology base, with no public funding commitment for near-term HBM expansion.
Caption: Use-of-funds allocation for CXMT IPO (Source: SemiAnalysis Memory Model; company reports)
A warning about cycle timing
The scale of profit fluctuations needs a reminder about timing in the cycle. CXMT’s IPO prospectus in December 2025 expected an attributable-to-parent loss of RMB 600 million to RMB 1.6 billion for 2025. Five months later, the updated prospectus reported a profit of RMB 1.87 billion, with consolidated profit more than twice the earlier high-end estimate. This also shows how quickly top pricing for DRAM can change the valuation denominator—both directions move the same way.
Alibaba’s dual role
One final detail: Alibaba’s changing role on CXMT’s list of shareholders has altered how the demand side is interpreted. Aliyun is both a core hyperscale customer and a roughly 4% shareholder/endorser, alongside Zhu Yiming’s GigaDevice (about 1.8% stake). In a sense, domestic demand volume at that scale has been secured—an advantage that the Korean giants did not have in their home markets. Though the percentage is small, the significance is much greater.
Note: The second half of this article contains paid in-depth analysis for SemiAnalysis regarding CXMT’s equipment ecosystem, the impact of export controls, and China’s memory and compute ambitions. It is not included in this compiled version.