In the semiconductor reverse engineering game, TechInsights has been the king for decades. Last weekend, Dylan Patel's SemiAnalysis officially dropped the first public teardown report from its STEEL lab (Teardown Engineering & Evaluation Lab), focusing on one of the hottest chips globally, the Huawei Mate 80 Pro equipped with the Kirin 9030 Pro, utilizing SMIC's cutting-edge N+3 process.
The timing is intriguing. TechInsights is on the block for private equity sale, while SemiAnalysis's revenue has already surpassed that of this veteran giant. Dylan chose to strike at this juncture with a highly technical teardown report, complemented by real chip photos from their Oregon lab.
The title of the report is a bombshell: SMIC N+3's minimum metal pitch (M0 pitch) is just 32.5nm, smaller than the 36nm used in Intel's latest Panther Lake processors using the 18A process.
Did SMIC achieve finer metal pitch than Intel without EUV lithography?
If this news is only analyzed by its title, it would be enough to set the entire semiconductor circle ablaze, but SemiAnalysis itself poured cold water on this in the second paragraph of the report, calling it a 'cherry picked metric,' a deliberately selected indicator.
This article will decode this teardown report for you.
Density catch-up comes at a high cost.
SMIC's N+3 process has indeed caught up to TSMC's N6 in transistor density.
The STEEL lab measured the Bohr density of N+3 through TEM (transmission electron microscopy) cross-sectional analysis and found it to be 113.4 MTr/mm², slightly higher than TSMC's N6 at 107.7 MTr/mm². The unit height shrank from 252nm in N+2 to 228nm, and the contact gate pitch (CGP) reduced from 63nm to 57nm. Taken together, these numbers mean that SMIC has achieved logic density at the mature 7nm level of TSMC without EUV.
What is the cost?
SMIC's M0 layer uses self-aligned quadruple patterning (SAQP), meaning a single photomask pattern undergoes four processes to achieve finer lines. TSMC's N6 requires only double patterning (SADP) on the same layer. Quadruple means more photomasks, higher overlay precision requirements, more complex process flows, and higher costs.
SemiAnalysis directly observed the costs of SAQP in the cross-sectional images: N+3's M0 trench exhibits a distinct inverted trapezoidal profile (the bottom is narrower than the top), with a clear accumulation layer at the trench bottom. This morphology aids in copper filling, but at a 32.5nm pitch, controlling the process becomes increasingly difficult.
Using an analogy that a trader would understand: SMIC is making bills of the same denomination, but the printing cost of each is several times that of TSMC, and the yield risk is higher. The density is the same, but the economics are completely different.
Kirin 9030: Squeezing every inch of silicon under constrained conditions.
Huawei's HiSilicon chip design capabilities tell a different story.
Looking at the chip area, the Kirin 9030 is almost the same size as the previous generation 9020 (about 140mm²), but it packs in more: the CPU upgraded from 1 big core + 3 medium cores to 1 big + 4 medium, the GPU compute units increased from 4 to 6, and the NPU gained another Tiny core, with all levels of cache expanded. The density boost from N+3 allows Huawei to fit more logic units into the same chip size.
In terms of performance, the STEEL lab referenced publicly available benchmark data, clearly positioning the Kirin 9030's GPU performance (Maleoon 935) roughly on par with 2022's flagship level, with a 3DMark WLE score improvement of 70% over the previous generation, slightly surpassing Snapdragon 8+ Gen 1, but lagging 2.4 to 2.6 times behind the current flagship Snapdragon 8 Elite Gen 5.
The situation with the CPU illustrates the issue more clearly. The big core TaiShan Prime's IPC (instructions per clock) is roughly at the level of Arm Cortex-X2, a design from 2021. Apple's M1 Firestorm core, released in 2020, still has an IPC that exceeds it by 35%. The latest Apple M5 P core has an IPC that is 60% higher, with absolute performance being 2.7 times greater.
The root of the gap lies not in design, but in process. Apple and Qualcomm use TSMC's N4 and N3P, which have inherent advantages on the voltage-frequency curve: more transistors can be packed into the same area, and higher frequencies can be achieved at the same power consumption. Huawei's core design level is on par with the industry leaders' previous generation but is trapped in manufacturing processes two generations behind.
When the process hits a wall, Huawei is ready to 'fold'.
The most forward-looking part of the report is Huawei's announcement of the τ scaling law and LogicFolding roadmap at the 2026 ISCAS conference.
Traditional semiconductor scaling advances in a two-dimensional plane: shrinking transistors and thinning metal lines. Moore's Law has been about this for decades. Huawei's proposed τ scaling shifts the optimization goal from spatial domains to temporal domains, focusing on reducing the time costs of data movement and processing, including transistor switching delays, signal propagation delays, and computing and storage delays.
LogicFolding is the engineering realization of this theory. Simply put, it's about splitting the same logic module into two layers, face-to-face stacked, connected through ultra-fine spacing hybrid bonding. The immediate benefit of this approach is the reduction of the longest signal paths. In modern chips, a significant portion of power consumption and delay is spent driving long lines and relay buffers. By folding logic vertically, the critical path shortens, allowing for higher frequencies and lower power consumption.
Huawei has proposed an aggressive roadmap: the big core frequency of the Kirin 9030 is 2.75GHz, and lab tests have already achieved 3.39GHz on samples, aiming for 5GHz by 2031 while pushing equivalent density to 295 MTr/mm², comparable to TSMC's 14A level.
SemiAnalysis remains vigilant about this. They point out that Huawei's density calculation method differs from traditional foundries: the density of 3D stacking is calculated based on packaging area, stacking multiple active logic layers together naturally yields higher numbers. If the same method is applied to AMD's MI450X (N2 top layer + N3P bottom layer), the theoretical density could reach 460.2 MTr/mm², far exceeding Huawei's 2031 target.
But the direction itself is worth noting. By taking this path, Huawei is essentially taking the 'foundry work' into the hands of system design companies under process constraints. AMD's V-Cache utilizes 3D stacking for cache, and AMD's MI350X moves I/O and interconnect to the bottom chip; Huawei aims to go further by separating the same logic block and distributing it vertically, which presents a completely different level of engineering challenge.
Export controls are reshaping the dimensions of competition.
SemiAnalysis's final conclusion is straightforward: export controls haven't stopped China's chip advancement but have changed the path and cost of that progress.
SMIC's N+3 proves that you can achieve N6-level logic density without EUV. However, this path is more costly, the processes are more complex, and the yield is harder to control. As you go further down this path, the marginal difficulty of each step increases: more photomasks, stricter overlay precision, and more expensive multi-patterning. Theoretically, N+4 can achieve 137.8 MTr/mm² (matched against TSMC's N5), and N+5 could approach Intel's 18A HP library if backside power delivery is included. But every step becomes harder, more expensive, and with less room for error.
Meanwhile, SMIC's N+2 and N+3 processes are being transferred to Huahong, with design companies like Alibaba's Pingtouge and Cambricon likely to benefit. Knowledge of chip manufacturing is spreading from a single foundry to an ecosystem, diluting the efficacy of sanctions targeting a single company.
On the design front, Huawei and Peking University are already developing domestic EDA tool prototypes for LogicFolding. This doesn't replace the full toolchain of Synopsys and Cadence, but domestic EDA is evolving towards "architecture-process-packaging collaborative optimization."
An interesting detail: during the teardown, STEEL found that the Kirin 9030 Pro's DRAM comes from Samsung (K4L2E165YD, LPDDR5X-9600, 1a process node), while the 16GB Pro Max version features both Samsung and Changxin Storage (CXMT) packaging. The packaging date for Changxin's chip is marked as week 45 of 2025, with process density comparable to the industry-leading 1z level. This means that Chinese storage chips are starting to enter Huawei's flagship supply chain, even though their process lags behind Samsung and SK Hynix by one to two generations.
For investors, the real signals worth tracking lie in whether Huawei's 3D stacking route can achieve a usable threshold for Chinese chips in mobile phones, AI inference, network devices, and other scenarios, all while keeping costs under control.
Once the usability is established, the strategic value of this supply chain will be re-evaluated.