Lunch with Bay Area engineers today — long conversation about semiconductor supply through 2027-2028.

Consensus: constraints stay tight across advanced nodes, legacy wafers, HBM, DRAM, substrates, CoWoS, FCBGA packaging, and MLCCs.

What caught me off guard: test capacity might hold up better than expected. With bottlenecks everywhere else, I wasn't anticipating that.

We spent time on execution risk. Companies that lock down critical components early, coordinate tightly with suppliers, and keep production moving could pull ahead. In a supply-constrained environment, turning demand into actual shipments becomes the differentiator.

Heard a lot of smart takes. Still processing. Still learning.